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part number 405EZ revision 1.27 - august 22, 2007 amcc proprietary 1 405EZ powerpc 405EZ embedded processor preliminary data sheet features ? amcc powerpc ? 405 32-bit risc processor core operating at up to 416mhz ? on-chip 32-bit peripheral bus (opb) operating at up to 83 mhz ? on-chip 64-bit processor local bus (plb) operating at up to 166mhz ? 8-bit direct interface for nand flash devices ? 32kb of on-chip, high-speed sram accessible by cpu and dma ? inter-chip connectivity (spi and iic) ? external 8-,16-, or 32-bit peripheral bus (ebc) operating at up to 83mhz ? boot from iic bootstrap controller, ebc, nand flash, and spi ? dma support for all on-chip slaves and external bus, including on-chip sram, adc, dac, uarts, and devices on the external peripheral bus ? one 10/100 mbps ethernet mii interface (half- and full-duplex) to external phy ? three usb 1.1 ports: two host and one device with full-speed on-chip phys ? programmable universal interrupt controller (uic) ? ieee 1588 precision timing protocol (ptp) controller ? chameleon timer ? and pulse width modulator (pwm) ? analog-to-digital converter (adc) with eight inputs and 10-bit resolution at 300k samples/sec ? digital-to-analog converter (dac) with one input and 10-bit resolution at 30m samples/sec ? two can 2.0b protocol and iso 11898-1 compliant channels ? two serial ports (16750 compatible uart) ? one iic interface operating at up to 400khz and supporting all standard iic eeproms ? one spi (scp) synchronous full-duplex channel operating at up to 40 mhz ? 54 general purpose i/os (gpios), each with programmable interrupts and outputs ? supports jtag for board-level testing ? system power mana gement, low power dissipation and small form factor ? rohs compliant (lead-free) description with speeds up to 416mhz, a flexible on-chip and off- chip memory architecture, a combination of an adc, a dac, a programmable chameleon timer/pwm, an ieee 1588 ptp, and a diverse communications package that includes usb 1.1, ethernet, and can, the powerpc 405EZ embedded processor provides a low power and small footprint system-on-a-chip solution for a wide range of high performance, cost- constrained embedded applications. this includes industrial control, high-p recision ac/dc and servo drive control, instrument ation, data acquisition, industrial automation, building and enclosure management, commercial and retail systems, internet appliances, and intelligent usb peripherals. it is an easily programmable general purpose, 32-bit risc controller that offers an upgrade path for applications in need of performance and connectivity improvements. technology: cu-11 cmos, 130nm package: 324-ball, 23mm 23mm, lead-free, plastic ball grid array (epbga), 1mm ball pitch typical power (est.): 1.05w @ 166 mhz;1.48w @ 416 mhz
ppc405EZ ? powerpc 405EZ embedded processor 2 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering, pvr, and jtag informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 power pc 405 processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 on-chip memory (ocm) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 nand flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 serial peripheral interface (spi/scp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 chameleon timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 general purpose i/o (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10/100 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ieee 1588 precision ti ming protocol controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 signal functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ratings and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 3 preliminary data sheet list of figures figure 1. ppc405EZ embedded controller functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. 23mm, 324-ball epbga core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. clocking waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 4. input setup and hold timing wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 5. output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 list of tables table 1. system memory address map (4gb system memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5. pin groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 6. signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8. package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 9. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10. input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. typical dc power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12. dc power supply loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 13. system clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 14. peripheral interface i/o clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. i/o specifications?all cpu speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. i/o specifications?416 mhz cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 17. strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ppc405EZ ? powerpc 405EZ embedded processor 4 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet ordering, pvr, and jtag information this section provides the part number nomenclature. fo r availability, contact your local amcc sales office. the part number contains a part modifier . included in the modifier is a revisi on code. this refers to the die mask revision number and is specified in the part num bering scheme for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniquely identifies the part. see the ppc405EZ embedded processor user?s manual for details about accessing these registers. order part number key product name order part number ( see notes:) package rev level pvr value jtag id ppc405EZ ppc405EZ-csaffftx 23mm, 324-ball, epbga a 0x41511460 0x0405a1e1 notes: 1. c = can enabled 2. s = lead-free epbga package (rohs compliant) 3. a = chip revision level a 4. fff = processor frequency 166 = 166mhz 266 = 266mhz 333 = 333mhz 416 = 416mhz 5. t = case temperature range, -40 c to +105 c 6. x = shipping package type z = tape-and-reel blank = tray amcc part number ppc405EZ-csa416tz package processor speed (mhz) can enabled case temperature range shipping package revision level note: the example p/n above is can enabled, lead -free, capable of running at 416mhz, and is shipped in tape-and-reel packaging.
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 5 preliminary data sheet block diagram figure 1. ppc405EZ embedded controller functional block diagram the ppc405EZ is designed using the ibm microelectronics blue logic tm methodology in which major functional blocks are integrated together to create an application-sp ecific asic product. this approach provides a consistent way to create complex asi cs using ibm coreconnect tm bus architecture. d-ocm i-ocm 32kb sram dcr gpio iic/ timer/ mal ethernet dma bridges clock control reset power mgmt jtag trace timers mmu mii controller opb/plb interrupt controller arbiter universal (4-channel) dcrs arbiter uart x2 can x2 spi usb 1.1 host/dev nand flash controller (scp) dac adc ocm ctrl 16kb i-cache 16kb d-cache on-chip peripheral bus (opb) processor local bus (plb) 64 bit, plb3 powerpc 405 core ieee external bus controller 10/100 1588 bus bsc pwm ptp phy
ppc405EZ ? powerpc 405EZ embedded processor 6 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet address maps the ppc405EZ incorporates two address maps. the first address map defines the possible use of addressable memory regions that the processor can access. the seco nd address map defines device configuration register (dcr) addresses (numbers). the dcrs are accessed by software running on the ppc405EZ processor through the use of mtdcr and mfdcr instructions. table 1. system memory address map (4gb system memory) function subfunction start address end address size general use 0x 0000 0000 0x dfff ffff 3.7gb reserved 0x e000 0000 0x ef60 02ff uart 0 registers 0x ef60 0300 0x ef60 03ff 256b uart 1 registers 0x ef60 0400 0x ef60 04ff 256b iic registers 0x ef60 0500 0x ef60 05ff 256b opb arbiter registers 0x ef60 0600 0x ef60 06ff 256b gpio 0 controller registers 0x ef60 0700 0x ef60 07ff 256b gpio 1 controller registers 0x ef60 0800 0x ef60 08ff 256b emac registers 0x ef60 0900 0x ef60 09ff 256b reserved 0x ef60 0a00 0x ef60 0fff can 0 registers 0x ef60 1000 0x ef60 17ff 2kb can 1 registers 0x ef60 1800 0x ef60 1fff 2kb chameleon timer registers 0x ef60 2000 0x ef60 27ff 2kb ieee 1588 sync controller regist ers 0x ef60 2800 0x ef60 2fff 2kb usb 1.1 host registers 0x ef60 3000 0x ef60 31ff 512b reserved 0x ef60 3200 0x ef60 32ff dac registers 0x ef60 3300 0x ef60 33ff 256b adc registers 0x ef60 3400 0x ef60 34ff 256b serial communication port registers 0x ef60 3500 0x ef60 35ff 256b reserved 0x ef60 3600 0x ef63 ffff usb 1.1 device registers 0x ef64 0000 0x ef67 ffff 262kb reserved 0x ef68 0000 0x ffdf ffff boot address range 0x ffe0 0000 0x ffff ffff 2 mb notes: 1. if peripheral bus boot is selected, peripheral bank 0 is au tomatically configured at reset to the address range listed above. 2. after the boot process, software may reas sign the boot memory regions for other uses.
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 7 preliminary data sheet table 2. dcr address map function start address end address size total dcr address space 1 0x000 0x3ff 1kw (4kb) 1 reserved 0x000 0x00b 12b cpr 0x00c 0x00d 2b sdr 0x00e 0x00f 2b reserved 0x010 0x011 2b ebc 0x012 0x013 2b reserved 0x014 0x01f 12b ocm controller 0x020 0x02f 16b reserved 0x030 0x07f 80b plb arbiter 0x080 0x08f 16b reserved 0x090 0x09f 16b plb-to-opb bridge 0x0a0 0x0a7 8b reserved 0x0a8 0x0af 8b opb-to-plb bridge 0x0b0 0x0b3 4b reserved 0x0b4 0x0b7 4b cpm 0x0b8 0x0bb 4b reserved 0x0bc 0x0bf 4b uic 0x0c0 0x0cf 16b reserved 0x0d0 0x0df 16b ieee 1588 snapshot source 0x0e0 0x0ef 16b reserved 0x0f0 0x0ff 16b dma 0x100 0x13f 64b reserved 0x140 0x2ff 578b mal 0x380 0x3ff 128b notes: 1. dcr address is 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bi t (word) register, or 1 ki loword (kw) (which equals 4 kb).
ppc405EZ ? powerpc 405EZ embedded processor 8 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet power pc 405 processor core the ppc405 core is a fixed-point, 32-bit risc processor. features include: ? five-stage pipeline with single-cycle execution of most instructions, in cluding loads and stores ? separate, configurable 16 kb d- and i-caches, both 2-way set associative ? thirty-two 32-bit general purpose registers (gprs) ? unaligned load/store support ? hardware multiply/divide ? parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (tlb) ? double word instruction fetch from cache ? translation of the 4gb logical address space into physical addresses ? on-chip memory (ocm) interface ? built-in timer and debug support ? power management ? 32-bit dcr interface internal buses the ppc405EZ contains three internal buses: the on-chip peripheral bus (opb), the processor local bus (plb), and the device control register (dcr) bus. high bandwidth devices such as the processor and the dma core utilize the plb. lower bandwidth i/o inte rfaces such as communications an d timer interfaces utilize the opb. opb the opb provides 32-bit address and data interfaces, and operates up to 83mhz. there is a bridge between the opb and the plb. features include: ? - pipelined read support ? - dynamic bus sizing ? - single-cycle data transfer between masters and slaves plb the processor local bus (plb) is a high-performance on-chip bus used to connect plb-equipped master and slave devices to the ppc405 cpu. it provides a 64-bit data path with 32-bit addressing and operates at up to166mhz. there is a bridge between the plb and the opb. features include: ? overlapping read and write transfers ? decoupled address and data buses ? address pipelining ? late master request abort capability ? hidden (overlapped) bus request/grant protocol ? bus arbitration-locking mechanism ? byte-enable capabilit y allows for unaligned half wo rd transfers and 3-b transfers ? support for 16-, 32-, and 64-b line data transfers ? read word address capability ? sequential burst protocol ? guarded and unguarded memory transfers ? dma buffered, flyby, peripheral-to-memory, memory-to-peripheral, and dma memory-to-memory operations
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 9 preliminary data sheet dcr bus the daisy-chained dcr bus provides a path for passing st atus and control information between the processor core and the other on-chip cores. all dcrs are 32 bits in width. on-chip memory (ocm) controller the ocm controller connects the 405EZ processor core to two non-overlapping banks of single-port, on-chip, configurable 32kb sram memory. the ocm can also trans fer data between the plb and internal sram banks. features include: ? simultaneous plb3, instruction-side ocm and data-side ocm access ? plb slave cycles support: ? 64-bit slave attachment addressable by any plb master ? single-beat read and write (1 to 8 bytes) ? 4-, 8-, and 16-word line read and write ? double word and word read and write bursts ? slave-terminated double word and word bursts ? master-terminated variable length bursts ? data parity generation and checking ? read/write protection per bank ? instruction side interface supports: ? one-wait state ocm access with 1-deep write buffer ? data parity checking ? data side interface supports: ? one-wait state ocm access with 1-deep write buffer ? data parity generation and checking ? read/write protection per bank ? processor side data port has highest access priori ty (maintains predictable memory accesses to ocm) external bus controller the external bus controller (ebc) transfers data between the plb and external memory or peripheral devices attached to the external peripheral bus. the ebc provides direct attachment of memory devices such as rom and sram, dma device paced memory de vices, and dma peripheral devices. features include: ? up to 83 mhz speed ? 8-, 16-, or 32-bit data bus, 28-bit address bus ? up to eight chip selects ? arbitration and multi-master supported ? flash rom interface ? boot from ebc (including nand flash interface) support ? direct support for 8-,16-, or 32-bit sram and external peripherals ? cram/psram support nand flash controller the nand flash controller (ndfc) prov ides a simple interface between the external bus controller (ebc) and a variety of nand flash-based storage devices. features include: ? attachment as internal ebc slave device (refer to the ppc405EZ embedded processor user?s manual for
ppc405EZ ? powerpc 405EZ embedded processor 10 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet more details) ? direct 8-bit interfacing to discrete nand flash devices ? up to four banks of nand flash supported ? device size 4mb-256mb (32mb to 2gb) supported ? 512b + 16b or 2kb + 64b device page sizes supported ? ecc generation - hamming code, single-bit correction, double-bit detection (sec/ded) ? eight-bit command write, address write, and data read/write ? interrupt on device ready (after long page write or block erase operations) ? boot from nand ? executes up to 4 kb of boot code out of first block ? automatic page read accesses performed based on device configuration and read address dma controller the direct memory access (dma) controller is a processo r local bus (plb) master that enables faster data transfer between memory and peripherals than is possib le under program control. the 4-channel dma controller handles data transfers between memory and peripherals and from memory-to-memory. each channel has an independent set of registers needed for data transfer: a c ontrol register, a source address register, a destination address register, and a transfer count register. features include: ? memory-to-memory transfers ? buffered memory-to-peripheral transfers ? buffered peripheral-to-memory transfers ? four independent dma channels ? scatter/gather capability for dynamically programming multip le dma transfers ? programmable address increment or decrement ? internal data buffering ? can transfer data to/from any plb and opb slave, including ocm and external bus usb interface the usb support provides separate host and device interfaces complia nt with the usb1.1 specification features include: ? usb1.1 host (2 ports) ? compliant with usb 1.1 specification and ohci version 1.0a host controller specification ? compatible with usb 2.0 full-speed peripherals ? supports low-speed (1.5mbps) operation ? all transfer types (isochronous, interrupt, control, and bulk) supported ? tx and rx fifos: 16-entries x 32-bits each ? independent 32-bit opb master and slave interfac es (master and slave can operate asynchronously) ? programmable opb slave base address ? up to 127 connected devices supported ? usb1.1 device (1 port) ? full- and low-speed device controller ? 32-bit, opb slave interface ? three endpoints supported (endpoint 0 is used for control) ? endpoints 1?2 can be in, out, in and out, in/out programmable ? endpoints 1?2 configurable to support interrupt/bulk only, isochronous only, interrupt/bulk or isochronous (programmable) transfer types ? endpoints 1?2 configurable to support maximum packet size of 8, 16, 32, or 64 bytes ? endpoint 0 configurable to support maximum packet size of 8 or 16 bytes ? full speed (12 mbps) usb phy for each of the 3 usb ports ? tolerates shorting to 5.25v and shorting to ground if driving signal conditions me et those specified in the
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 11 preliminary data sheet universal serial bus specification controller area network (can) the can controller module supports the concept of mailb oxes. it contains 32 receive buffers, each one with its own message filter, and 32 transmit buffers with a prioritized arbitration scheme. for optimal support of higher level protocols (hlp) such as devicenet or sdc, the message filter covers the first two data bytes. features include: ? can 2.0b protocol compliant ? iso 11898-1 compliant ? 32 transmit message holding registers, programmable priority arbitration ? message abort command supported ? 32 receive buffers (each with own message filter) ? message filtering: id, ide, remote transmission request (rtr), data byte 1, and data byte 2 ? message buffers can be linked together to build bigger message arrays ? automatic rtr response handler ? message abort command supported ? maximum baud rate of 1mbps with 8mhz system clock ? listen-only for debugging supported ? global masking supported ? 32-bit opb slave interface ? internal loopback uart the universal asynchronous receiver/transmitter (uart) interface provides two ports. the uart performs serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the processor. features include: ? two ports (uart_0 and uart_1) ? software modem control functions (cts, rts, dsr, dtr, ri, dcd) on uart_0 ? programmable auto flow (data flow controlled by rts and cts signals) ? 5-, 6-, 7-, or 8-bit characters ? programmable start, stop, parity bit insertion ? 64 byte fifos to buffer tx and rx data ? lin sub-bus specification compliant - line break generation/detection and false start bit detection ? programmable internal/ext ernal loopback capabilities ? low power and sleep mode ? register conformance (after reset) to configuration of the ns16450 register set ? hold and shift registers (eliminate need for precise synchronization between processor and serial data in character mode) ? complete status reporting ? full prioritized inte rrupt system controls ? independently controlled transmit, receiv e, line status, and data set interrupts ? programmable baud generator (divides seri al clock input and generates 16x clock) ? ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial data ? even, odd, or no-parity bit generation and detection ? 1-, 1.5-, or 2-stop bit generation ? variable baud rate ? internal diagnostic capability
ppc405EZ ? powerpc 405EZ embedded processor 12 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet ? loopback controls for isolating communications link faults ? break, parity, overrun, framing error simulation ? opb interface with optional dma support iic bus interface the inter-integrat ed circuit (iic) interface provides a philips i 2 c ? compatible interface operating up to 400khz either as a master, a slave, or both with a bootstrap c ontroller (bsc) included. during chip reset, the bootstrap controller can read conf iguration data from an iic co mpatible memory device (e.g ., eeprom). this data can be used to replace the default configurat ion settings provided by the chip. features include: ? one iic channel ? compliant with philips semiconductors i 2 c specification , dated 1995 ? 100 khz or 400 khz operation ?8-bit data ? 10- or 7-bit address ? slave transmit and receive ? master transmit and receive ? multiple bus masters supported ? programmable as master, slave, or master/slave ? boot parameters read from iic attached memory with iic bootstrap controller ? 32-bit opb slave interface serial peripheral interface (spi/scp) the serial peripheral interface (spi) (also known as the serial communications port or scp) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. the spi is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock) , and is a slave on the opb. features include: ? one spi/scp channel, full duplex synchronous ? spi/scp master ? up to 40 mhz ? programmable internal loopback capabilities ? multi-master protocol supported ? independent masking of all in terrupts (master collision, tr ansmit fifo overflow, tran smit fifo empty, receive fifo full, receive fifo under flow, receive fifo overflow) ? dynamic control of serial bit rate of data transfer (serial-master mode only) ? data item size for each data transfer under programmer control (4-to-16 bits) ? boot from spi supported ? 32-bit opb slave interface
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 13 preliminary data sheet chameleon timer the chameleon timer?s timer service engine (tse) controls the local timer ram config ured as 120 32-bit words and up to fifteen 24-bit timer channel s, each with an input capture register or an output compare register. the chameleon timer interfaces to the opb. features include: ? pulse width modulation (pwm) and space ve ctor pwm functions with non-overlap times ? programmable ?deadband? intervals ? pulse period measurement ? 48-bit input capture function ? 48-bit output compare function ? ieee1588 time stamps ? automatic up, down, and up-then-down counting with modulus ? autonomous timer service engine (tse) manages timer channels ? cpu programs ?registers? in timer sram (120x32 bits) ? 15 timer channels + 1 timebase channel ? pulse period measurements ? configurable for seven 48-bit channels or 15 24-bit channels ? up to two timebases available simultaneously ? each time base has four optional sources: three internal (timebase a, timebase b, and ieee1588) and one external ? speed/resolution: 166mhz counter, 2-clock (20ns) minimum period ? latency: 0.49 sec worst case (based on 133mhz system clock) ? external ?fault? pin to automatica lly disable timer channel outputs ? low emc switching noise ? unused timer i/o pins available for gpio use ? 32-bit opb slave interface general purpose i/o (gpio) controller the gpio controller enables multiplexing of module i/o pins wi th multiple functions within the chip. that is, a single package pin can be assigned to multiple i/o functions. which function the pin is as signed to is determined by register bit settings controlled by software. this signif icantly reduces the number of package pins needed to support multiple i/o groups. features include: ? up to 54 gpios available ? gpios are multiplexed with alternate functions ? if not in use for dedicated functions, i/os are available as gpios ? direct control of all functions from registers programmed by means of opb bus master accesses ? time multiplexing of controller outputs to module outputs ? programmable conversion of module outputs to open-dr ain outputs (enables sharing of active low outputs externally) ? time multiplexing of module inputs to controller inputs
ppc405EZ ? powerpc 405EZ embedded processor 14 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet universal interrupt controller (uic) the universal interrupt controller (uic) provides the co ntrol, status, and communica tions necessary between the various sources of interrupts and the ppc405 processor. features include: ? 32 interrupt sources supported (5 external) ? generate interrup t on level (high or low) or edge (rising or falling) ? programmable as synchronous (edge-capture or level-se nsitive) or asynchronous (edge- or level-sensitive triggering) ? each interrupt source/bit programmable as critical or non critical ? 32-bit dcr bus interface ? optional interrupt handler vector generation ? programmable vector base address ? programmable vector offset size ? programmable interrupt priority ordering ? programmable polarity for all interrupt types ? interrupts of the same type do not need to be in contiguous bit positions ? status registers provide: current state of all interrupts, current state of enabled interrupts 10/100 ethernet the ethernet support provides a single 10/100 mbps interface. features include: ? ansi/ieee std. 802.3 and i eee 802.3u supple ment compliant ? half-duplex and full-duplex supported ? mii interface to external phy ? 512 byte receive fifos with programmable thresholds ? fcs control for transmit/receive packets ? multiple packet handling in transmit and receive fifos ? unicast, multicast, broadcast, and promiscuous address filtering ? two 64-bit hash filters fo r unicast and multicast frames ? automatic retransmission of collided frames ? runt frame rejection ? programmable inter-frame gap ? ieee 802.3x compliant for frame-based flow control mechanism, including self-a ssembled control frame transmitting) ? wake-on-lan and power-over-internet supported ? programmable internal/ext ernal loopback capabilities ? 32-bit opb slave (mac) and plb master (mal) interfaces ? extensive error/status vector ge neration for each processed packet ? vlan tag id supported (according to ieee draft 802.3ac/d1.0 standard) ? programmable automatic source address in clusion/replacement for transmit packets ? programmable automatic pad/fcs stripping for receive packets ? programmable vlan tag inclusion/replacement for transmit packets ieee 1588 precisi on timing protocol controller in a distributed control system containi ng multiple clocks, this feature defin es messages used to exchange timing information for precision network synchronization purposes. a second uic in the ppc405EZ is dedicated to generating snapsh ot triggers to the ieee 1588 ptp controller from any inte rrupt source in the chip.
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 15 preliminary data sheet analog-to-digital converter (adc) the adc is a mixed-signal core. it us es the successive approximation (binary search) conversion technique to achieve minimal conversion time. the an alog input range is 0.0v to vref. features include: ? internal 10-bit resolution sar adc ? sample and hold ? support for multiple conversion times such as ?3.25 s with 4-mhz input clock ?52 s with 250-khz input clock ?comparator ? digital controller ? 8-channel analog input (3.3 v) with 8:1 analog multiplexer ? 10-bit parallel digital outputs ? input trigger from chameleon timer supported ? opb interface with optional dma support digital-to-analog converter (dac) the dac is a 1-channel converter, opt imized for low power applications. it provides unbuffered single-ended analog current output. the single analog current output can be tied directly to an output resistor to provide twos- complementary, single-ended voltage outputs. features include: ? 10-bit resolution at 30m samples/sec ? segmented dac ? single-ended current outputs (6ma maximum swing at 3.3v) ? monotonicity ensured ? straight binary input ? internal bandgap voltage reference ? power management by means of sleep mode ? integrated functional test logic ? input trigger from chameleon timer supported ? opb interface with optional dma support jtag features include: ? ieee 1149.1 te st access port ? jtag boundary scan description language (bsdl) refer to http://www.amcc.com/embedded/partners for a list of amcc partners supplying probes for use with the jtag interface.
ppc405EZ ? powerpc 405EZ embedded processor 16 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet figure 2. 23mm, 324-ball epbga core top view bottom view a 1.0 typ 23.0 23.0 b c d e f g h j k l m aa n p r t u v w y ab 01 03 05 07 09 11 13 15 17 19 02 04 06 08 10 12 14 16 18 21 20 22 21.0 0.3 ? 0.6 pcb substrate epoxy mold compound 2.65 max gold gate release corresponds to a01 ball location ? ppc405EZ 1ywwbzzzzz part number lot number logo view notes: 1. all dimensions are in mm. 2. package is lead-free (rohs compliant) 3. package conforms to jedec spec.ms-034 0.60 0.1 solderball x 324
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 17 preliminary data sheet signal lists the following table lists all the external signals in alphab etical order and shows the ball (pin) number on which the signal appears. multiplexed signals are show n with the default signal (following reset) not in brackets and the alternate signal in brackets. multiplexed signals appear al phabetically multiple times in the list?once for each signal name on the ball. the page column indicates the p age within the table ?signal functional description? on page 35 on which the signals in the indicated interface group begin. table 3. signals listed alphabetically (sheet 1 of 11) signal name ball interface group page adc_agnd ab07 power 40 adc_av dd ab08 adc_in0 t01 analog to digital converter (adc) 37 adc_in1 u01 adc_in2 w01 adc_in3 y01 adc_in4 aa01 adc_in5 ab02 adc_in6 ab03 adc_in7 ab04 adc_intrig[ts6][gpio109] u04 adc_vref ab06 busreq[gpio007] d20 external peripheral 38 can0_rx c02 controller area network 37 can0_tx b03 can0_txe c01 can1_rx c04 can1_tx b04 can1_txe a03 cram_adv [gpio010] b22 external peripheral 38 cram_clk[gpio008] f19 dac_agnd a07 power 40 dac_av dd a08 dac_cref b08 digital to analog converter (dac) 37 dac_gref b07 dac_ioutp a06 dac_iptrig[ts5][gpio108] c08 dac_irref b09 dac_vref b06 debugen c17 system 49 dmaack [gpio027] a19 external peripheral 38 dmaeot/tc [gpio026] a20 dmareq [gpio025] c19 emccol u02 ethernet 35 emccrs j04 emcmdc r03 emcmdio n03
ppc405EZ ? powerpc 405EZ embedded processor 18 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet emcrxclk m01 ethernet 35 emcrxdv r01 emcrxd0 l02 emcrxd1 l01 emcrxd2 m02 emcrxd3 n01 emcrxer m03 emctxclk r02 ethernet 35 emctxd0 n02 emctxd1 p02 emctxd2 p03 emctxd3 p04 emctxen u03 emctxer t02 table 3. signals listed alphabetically (sheet 2 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 19 preliminary data sheet gnd a01 power 40 gnd a02 gnd a05 gnd a09 gnd a14 gnd a18 gnd a22 gnd b02 gnd b21 gnd c03 gnd c09 gnd c20 gnd d04 gnd d06 gnd d08 gnd d09 gnd d12 gnd d15 gnd d19 gnd e01 gnd e22 gnd h04 gnd h19 gnd j01 gnd j09 gnd j11 gnd j12 gnd j14 gnd j22 gnd k10 gnd k11 gnd k13 gnd l04 gnd l09 gnd l11 gnd l12 gnd l13 gnd l14 table 3. signals listed alphabetically (sheet 3 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor 20 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet gnd m09 power 40 gnd m10 gnd m11 gnd m12 gnd m14 gnd m19 gnd n10 gnd n12 gnd n13 gnd p01 gnd p09 gnd p11 gnd p12 gnd p14 gnd p22 gnd r04 gnd r19 gnd v01 gnd v22 gnd w04 gnd w06 gnd w08 gnd w09 gnd w11 gnd w15 gnd w19 gnd y03 gnd y06 gnd y20 gnd aa02 gnd aa04 gnd aa05 gnd aa21 gnd ab01 gnd ab05 gnd ab09 gnd ab14 gnd ab18 gnd ab22 table 3. signals listed alphabetically (sheet 4 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 21 preliminary data sheet [gpio000]percs4 g20 system 49 [gpio001]percs5 [nfce1 ]f20 [gpio002]percs6 [nfce2 ]f21 [gpio003]percs7 [nfce3 ]e21 [gpio004]holdreq d22 [gpio005]holdpri d21 [gpio006]holdack c22 [gpio007]busreq d20 [gpio008]cram_clk f19 [gpio009]perready c21 [gpio010]cram_adv b22 [gpio011]nfcle w03 [gpio012]nfdata7 aa03 [gpio013]nfdata6 y02 [gpio014]nfdata5 y04 [gpio015]nfdata4 y05 [gpio016]nfdata3 aa06 [gpio017]nfdata2 y07 [gpio018]nfdata1 aa07 [gpio019]nfdata0 y08 [gpio020]nfale aa08 [gpio021]nfce0 y09 [gpio022]nfre aa09 [gpio023]nfwe y10 [gpio024]nfrb aa10 [gpio025]dmareq c19 [gpio026]dmaeot/tc a20 [gpio027]dmaack a19 [gpio028]pwm_oe1[ts1o] b15 [gpio029]pwm_oe2[ts2o] a15 [gpio030]pwm_oe3[ts3] c13 [gpio031]pwm_8 c11 table 3. signals listed alphabetically (sheet 5 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor 22 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet [gpio100]pwm_9 a10 system 49 [gpio101]pwm_10 b10 [gpio102]pwm_11 c10 [gpio103]pwm_12 c06 [gpio104]pwm_13 c07 [gpio105]pwm_14 b05 [gpio106]pwm_15 c05 [gpio107]pwm_divclk[irq4] a04 [gpio108]dac_iptrig[ts5] c08 [gpio109]adc_intrig[ts6] u04 [gpio110]uart0_dcd d02 [gpio111]uart0_dsr d01 [gpio112]uart0_cts e03 [gpio113]uart0_dtr [tmrclk][ieee_1588ts] f04 [gpio114]uart0_rts [spi_ss_2] f03 [gpio115]uart0_ri [spi_ss_3] e02 [gpio116][spi_ss_in ]spi_ss1 d14 [gpio117]irq0[trcclk] t03 [gpio118]irq1[ts1e] v02 [gpio119]irq2[ts2e] v03 [gpio120]irq3[ts4] w02 gpio121 c14 halt c18 system 36 holdack[gpio006] c22 external peripheral 38 holdpri [gpio005] d21 holdreq [gpio004] d22 [ieee_1588ts]uart0_dtr [tmrclk][gpio113] f04 ieee 1588 network synchronization 35 iic0sclk b16 iic peripheral 35 iic0sdata c15 irq0[trcclk][gpio117] t03 interrupt 35 irq1[ts1e][gpio118] v02 irq2[ts2e][gpio119] v03 irq3[ts4][gpio120] w02 [irq4]pwm_divclk[gpio107] a04 nfale[gpio020] aa08 nand flash 38 nfce0 [gpio021] y09 nand flash 38 [nfce1 ]percs5 [gpio001] f20 [nfce2 ]percs6 [gpio002] f21 [nfce3 ]percs7 [gpio003] e21 nfcle[gpio011] w03 nfdata0[gpio019] y08 nand flash 38 nfdata1[gpio018] aa07 nfdata2[gpio017] y07 nfdata3[gpio016] aa06 nfdata4[gpio015] y05 nfdata5[gpio014] y04 nfdata6[gpio013] y02 nfdata7[gpio012] aa03 table 3. signals listed alphabetically (sheet 6 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 23 preliminary data sheet nfrb[gpio024] aa10 nand flash 38 nfre [gpio022] aa09 nfwe [gpio023] y10 ov dd 1 d05 power 40 ov dd 1 d07 ov dd 1 d11 ov dd 1 d16 ov dd 1 d18 ov dd 1 e04 ov dd 1 g04 ov dd 1 j10 ov dd 1 j13 ov dd 1 k09 ov dd 1 m04 ov dd 1 n09 ov dd 1 p10 ov dd 1 t04 ov dd 1 v04 ov dd 1 w05 ov dd 1 w07 ov dd 2 e19 power 40 ov dd 2 g19 ov dd 2 k14 ov dd 2 l19 ov dd 2 n14 ov dd 2 p13 ov dd 2 t19 ov dd 2 v19 ov dd 2 w12 ov dd 2 w16 ov dd 2 w18 table 3. signals listed alphabetically (sheet 7 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor 24 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet peraddr04 u19 external peripheral 38 peraddr05 v20 peraddr06 w21 peraddr07 w22 peraddr08 u20 peraddr09 v21 peraddr10 u21 peraddr11 u22 peraddr12 t20 peraddr13 t21 peraddr14 t22 peraddr15 r20 peraddr16 p19 peraddr17 r21 peraddr18 r22 peraddr19 p20 peraddr20 p21 peraddr21 n20 peraddr22 n21 peraddr23 n22 peraddr24 m20 peraddr25 m21 peraddr26 m22 peraddr27 l22 peraddr28 l21 peraddr29 l20 peraddr30 k22 peraddr31 k21 perclk k20 external peripheral 38 percs0 h20 percs1 g22 percs2 g21 percs3 f22 percs4 [gpio000] g20 percs5 [nfce1 ][gpio001] f20 percs6 [nfce2 ][gpio002] f21 percs7 [nfce3 ][gpio003] e21 table 3. signals listed alphabetically (sheet 8 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 25 preliminary data sheet perdata00 y11 external peripheral 38 perdata01 aa11 perdata02 aa12 perdata03 ab13 perdata04 y12 perdata05 aa13 perdata06 ab15 perdata07 y13 perdata08 aa14 perdata09 aa15 perdata10 ab16 perdata11 y14 perdata12 w14 perdata13 ab17 perdata14 y15 perdata15 aa16 perdata16 y16 perdata17 aa17 perdata18 aa18 perdata19 y17 perdata20 y18 perdata21 ab19 perdata22 w17 perdata23 aa19 perdata24 ab20 perdata25 y19 perdata26 aa20 perdata27 ab21 perdata28 y22 perdata29 aa22 perdata30 y21 perdata31 w20 peroe e20 external peripheral 38 perready[gpio009] c21 external peripheral 38 perrw j21 external peripheral 38 perwbe0 j20 external peripheral 38 perwbe1 h22 perwbe2 j19 perwbe3 h21 pll_agnd ab11 power 40 pll_av dd ab12 pwm_divclk[irq4][gpio 107] a04 chameleon timer 36 pwm_oe0 a16 chameleon timer 36 pwm_oe1[ts1o][gpio028] b15 pwm_oe2[ts2o][gpio029] a15 pwm_oe3[ts3][gpio030] c13 pwm_tba b14 table 3. signals listed alphabetically (sheet 9 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor 26 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet pwm_1 b13 chameleon timer 36 pwm_2 c12 pwm_3 b12 pwm_4 a13 pwm_5 a12 pwm_6 a11 pwm_7 b11 pwm_8[gpio031] c11 pwm_9[gpio100] a10 pwm_10[gpio101] b10 pwm_11[gpio102] c10 pwm_12[gpio103] c06 pwm_13[gpio104] c07 pwm_14[gpio105] b05 pwm_15[gpio106 c05 reserved b19 other pins 40 spi_clkout b17 serial peripheral 38 spi_di d17 spi_do c16 spi_ss0 a17 spi_ss1 [spi_ss_in ][gpio116] d14 [spi_ss2 ]uart0_rts [gpio114] f03 [spi_ss3 ]uart0_ri [gpio115] e02 [spi_ss_in ]spi_ss1 [gpio116] d14 sysclk ab10 system 36 syserr b20 sysreset b18 tck h01 jtag 35 tdi l03 tdo k03 testen a21 tms g02 jtag 35 [tmrclk]uart0_dtr[ieee1588ts][gpio113] f04 system 36 [trcclk]irq0[gpio117] t03 trace 36 trst g01 jtag 35 [ts1e]irq1[gpio118] v02 trace 36 [ts2e]irq2[gpio119] v03 [ts1o]pwm_oe1[gpio028] b15 [ts2o]pwm_oe2[gpio029] a15 [ts3]pwm_oe3[gpio030] c13 [ts4]irq3[gpio120] w02 [ts5]dac_iptrig[gpio108] c08 [ts6]adc_intrig[gpio109] u04 table 3. signals listed alphab etically (sheet 10 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 27 preliminary data sheet uart0_cts [gpio112] e03 uart peripheral 39 uart0_dcd [gpio110] d02 uart0_dsr [gpio111] d01 uart0_dtr [tmrclk][ieee_1588ts][gpio113] f04 uart0_ri [spi_ss_3] [gpio115] e02 uart0_rts [spi_ss_2] [gpio114] f03 uart0_rx b01 uart0_tx d03 uart1_rx f02 uart peripheral 39 uart1_tx f01 usb_fclk g03 usb 39 usb1dev0 k02 usb1dev0 k01 usb1host0 h03 usb1host0 h02 usb1host1 j03 usb1host1 j02 v dd d10 power 40 v dd d13 v dd k04 v dd k12 v dd k19 v dd l10 v dd m13 v dd n04 v dd n11 v dd n19 v dd w10 v dd w13 table 3. signals listed alphabetically (sheet 11 of 11) signal name ball interface group page
ppc405EZ ? powerpc 405EZ embedded processor 28 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet in the following table, only the primary (default) signal name is shown for each ball. multiplexed or multifunction signals are marked with an asterisk (*). to determine what signals or functions are multiplexed on those balls, look up the primary signal name in ?signals listed alphabetica lly? on page 17.the following table lists the signals by ball assignment. table 4. signals listed by ball assignment (sheet 1 of 6) ball signal name ball signal name ball signal name ball signal name a01 gnd b01 uart0_rx c01 can0_txe d01 uart0_dsr * a02 gnd b02 gnd c02 can0_rx d02 uart0_dcd * a03 can1_txe b03 can0_tx c03 gnd d03 uart0_tx a04 pwm_divclk* b04 can1_tx c04 can1_rx d04 gnd a05 gnd b05 pwm_14* c05 pwm_16* d05 ov dd 1 a06 dac_ioutp b06 dac_vref c06 pwm_12* d06 gnd a07 dac_agnd b07 dac_gref c07 pwm_13* d07 ov dd 1 a08 dac_av dd b08 dac_cref c08 dac_iptrig* d08 gnd a09 gnd b09 dac_irref c09 gnd d09 gnd a10 pwm_9* b10 pwm_10* c10 pwm_11* d10 vdd a11 pwm_6 b11 pwm_7 c11 pwm_8* d11 ov dd 1 a12 pwm_5 b12 pwm_3 c12 pwm_2 d12 gnd a13 pwm_4 b13 pwm_1 c13 pwm_oe3* d13 v dd a14 gnd b14 pwm_tba c14 gpio121 d14 spi_ss1 * a15 pwm_oe2* b15 pwm_oe1* c15 iic0sdata d15 gnd a16 pwm_oe0 b16 iic0sclk c16 spi_do d16 ov dd 1 a17 spi_ss0 b17 spi_clkout c17 debugen d17 spi_di a18 gnd b18 sysreset c18 halt d18 ov dd 1 a19 dmaack * b19 reserved c19 dmareq * d19gnd a20 dmaeot/tc * b20 syserr c20 gnd d20 busreq* a21 testen b21 gnd c21 perready* d21 holdpri * a22 gnd b22 cram_adv * c22 holdack* d22 holdreq *
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 29 preliminary data sheet e01 gnd f01 uart1_tx g01 trst h01 tck e02 uart0_ri * f02 uart1_rx g02 tms h02 usb1host0 e03 uart0_cts * f03 uart0_rts * g03 usb_fclk h03 usb1host0 e04 ov dd 1 f04 uart0_dtr * g04 ov dd 1 h04 gnd e05 no ball f05 no ball g05 no ball h05 no ball e06 no ball f06 no ball g06 no ball h06 no ball e07 no ball f07 no ball g07 no ball h07 no ball e08 no ball f08 no ball g08 no ball h08 no ball e09 no ball f09 no ball g09 no ball h09 no ball e10 no ball f10 no ball g10 no ball h10 no ball e11 no ball f11 no ball g11 no ball h11 no ball e12 no ball f12 no ball g12 no ball h12 no ball e13 no ball f13 no ball g13 no ball h13 no ball e14 no ball f14 no ball g14 no ball h14 no ball e15 no ball f15 no ball g15 no ball h15 no ball e16 no ball f16 no ball g16 no ball h16 no ball e17 no ball f17 no ball g17 no ball h17 no ball e18 no ball f18 no ball g18 no ball h18 no ball e19 ov dd 2 f19 cram_clk* g19 ov dd 2 h19 gnd e20 peroe f20 percs5 * g20percs4 * h20 percs0 e21 percs7 * f21percs6 * g21percs2 h21 perwbe3 e22 gnd f22 percs3 g22 percs1 h22 perwbe1 table 4. signals listed by ball assignment (sheet 2 of 6) ball signal name ball signal name ball signal name ball signal name
ppc405EZ ? powerpc 405EZ embedded processor 30 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet j01 gnd k01 usb1dev0 l01 emcrxd1 m01 emcrxclk j02 usb1host1 k02 usb1dev0 l02 emcrxd0 m02 emcrxd2 j03 usb1host1 k03 tdo l03 tdi m03 emcrxer j04 emccrs k04 v dd l04 gnd m04 ov dd 1 j05 no ball k05 no ball l05 no ball m05 no ball j06 no ball k06 no ball l06 no ball m06 no ball j07 no ball k07 no ball l07 no ball m07 no ball j08 no ball k08 no ball l08 no ball m08 no ball j09 gnd k09 ov dd 1 l09 gnd m09 gnd j10 ov dd 1 k10 gnd l10 v dd m10 gnd j11 gnd k11 gnd l11 gnd m11 gnd j12 gnd k12 v dd l12 gnd m12 gnd j13 ov dd 1 k13 gnd l13 gnd m13 v dd j14 gnd k14 ov dd 2 l14 gnd m14 gnd j15 no ball k15 no ball l15 no ball m15 no ball j16 no ball k16 no ball l16 no ball m16 no ball j17 no ball k17 no ball l17 no ball m17 no ball j18 no ball k18 no ball l18 no ball m18 no ball j19 perwbe2 k19 v dd l19 ov dd 2 m19 gnd j20 perwbe0 k20 perclk l20 peraddr29 m20 peraddr24 j21 perrw k21 peraddr31 l21 peraddr28 m21 peraddr25 j22 gnd k22 peraddr30 l22 peraddr27 m22 peraddr26 table 4. signals listed by ball assignment (sheet 3 of 6) ball signal name ball signal name ball signal name ball signal name
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 31 preliminary data sheet n01 emcrxd3 p01 gnd r01 emcrxdv t01 adc_in0 n02 emctxd0 p02 emctxd1 r02 emctxclk t02 emctxer n03 emcmdio p03 emctxd2 r03 emcmdc t03 irq0* n04 v dd p04 emctxd3 r04 gnd t04 ov dd 1 n05 no ball p05 no ball r05 no ball t05 no ball n06 no ball p06 no ball r06 no ball t06 no ball n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 ov dd 1 p09 gnd r09 no ball t09 no ball n10 gnd p10 ov dd 1 r10 no ball t10 no ball n11 v dd p11 gnd r11 no ball t11 no ball n12 gnd p12 gnd r12 no ball t12 no ball n13 gnd p13 ov dd 2 r13 no ball t13 no ball n14 ov dd 2 p14 gnd r14 no ball t14 no ball n15 no ball p15 no ball r15 no ball t15 no ball n16 no ball p16 no ball r16 no ball t16 no ball n17 no ball p17 no ball r17 no ball t17 no ball n18 no ball p18 no ball r18 no ball t18 no ball n19 v dd p19 peraddr16 r19 gnd t19 ov dd 2 n20 peraddr21 p20 peraddr19 r20 peraddr15 t20 peraddr12 n21 peraddr22 p21 peraddr20 r21 peraddr17 t21 peraddr13 n22 peraddr23 p22 gnd r22 peraddr18 t22 peraddr14 table 4. signals listed by ball assignment (sheet 4 of 6) ball signal name ball signal name ball signal name ball signal name
ppc405EZ ? powerpc 405EZ embedded processor 32 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet u01 adc_in1 v01 gnd w01 adc_in2 y01 adc_in3 u02 emccol v02 irq1* w02 irq3* y02 nfdata6* u03 emctxen v03 irq2* w03 nfcle* y03 gnd u04 adc_intrig* v04 ov dd 1 w04 gnd y04 nfdata5* u05 no ball v05 no ball w05 ov dd 1 y05 nfdata4* u06 no ball v06 no ball w06 gnd y06 gnd u07 no ball v07 no ball w07 ov dd 1 y07 nfdata2* u08 no ball v08 no ball w08 gnd y08 nfdata0* u09 no ball v09 no ball w09 gnd y09 nfce0 * u10 no ball v10 no ball w10 v dd y10 nfwe * u11 no ball v11 no ball w11 gnd y11 perdata00 u12 no ball v12 no ball w12 ov dd 2 y12 perdata04 u13 no ball v13 no ball w13 v dd y13 perdata07 u14 no ball v14 no ball w14 perdata12 y14 perdata11 u15 no ball v15 no ball w15 gnd y15 perdata14 u16 no ball v16 no ball w16 ov dd 2 y16 perdata16 u17 no ball v17 no ball w17 perdata22 y17 perdata19 u18 no ball v18 no ball w18 ov dd 2 y18 perdata20 u19 peraddr04 v19 ov dd 2 w19 gnd y19 perdata25 u20 peraddr08 v20 peraddr05 w20 perdata31 y20 gnd u21 peraddr10 v21 peraddr09 w21 peraddr06 y21 perdata30 u22 peraddr11 v22 gnd w22 peraddr07 y22 perdata28 table 4. signals listed by ball assignment (sheet 5 of 6) ball signal name ball signal name ball signal name ball signal name
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 33 preliminary data sheet aa01 adc_in4 ab01 gnd aa02 gnd ab02 adc_in5 aa03 nfdata7* ab03 adc_in6 aa04 gnd ab04 adc_in7 aa05 gnd ab05 gnd aa06 nfdata3* ab06 adc_vref aa07 nfdata1* ab07 adc_agnd aa08 nfale* ab08 adc_av dd aa09 nfre * ab09 gnd aa10 nfrb* ab10 sysclk aa11 perdata01 ab11 pll_agnd aa12 perdata02 ab12 pll_av dd aa13 perdata05 ab13 perdata03 aa14 perdata08 ab14 gnd aa15 perdata09 ab15 perdata06 aa16 perdata15 ab16 perdata10 aa17 perdata17 ab17 perdata13 aa18 perdata18 ab18 gnd aa19 perdata23 ab19 perdata21 aa20 perdata26 ab20 perdata24 aa21 gnd ab21 perdata27 aa22 perdata29 ab22 gnd table 4. signals listed by ball assignment (sheet 6 of 6) ball signal name ball signal name ball signal name ball signal name
ppc405EZ ? powerpc 405EZ embedded processor 34 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet pin group list the following table provides a summary of the number of package pins (balls) associated with each functional interface group. in the table ?signal functional description? on page 35, eac h external signal is listed along with a short description of the signal function. active-l ow signals (for example, halt ) are marked with an overline. see the preceding table, ?signals listed alphabetically? on page 17, for the pin (ball) number to which each signal is assigned. multiplexed pins some signals are multiplexed on the same package pin so th at the pin can be used for different functions. in most cases, the signal names shown in this table are not ac companied by signal names that may be multiplexed on the same pin. if you need to know what, if any, signals are multiplexed with a pa rticular signal, look up the name in ?signals listed alphabetica lly? on page 17. it is expected that in any single application a particular pin will always be programmed to serve the same functi on. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. initialization strapping one group of pins is used as strapped inputs during syst em reset. these pins function as strapped inputs only during reset and are used for other functions during normal operation (see ?initialization? on page 51). note that the use of these pins for strapping is not considered mult iplexing since the strapping function is not programmable. pull-up and pull-down resistors pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. the recommended pull-up value of 3k to +3.3v and pull- down value of 1k to gnd, applies only to individually terminated signals. to prevent possi ble damage to the device, i/os capable of becoming outputs must never be tied together and terminated through a common resistor. if your system-level test methodology permits, input- only signals can be connected together and terminated through either a common resistor or directly to +3.3v or g nd. when a resistor is used, its value must ensure that the grouped i/os reach a valid logic zero or logic one state when accounting for the total input current into the ppc405EZ. table 5. pin groups group no. of pins total signal pins 200 v dd 12 ov dd 1 17 ov dd 2 11 gnd 77 adc_av dd 1 adc_gnd 1 dac_av dd 1 dac_gnd 1 pll_av dd 1 pll_gnd 1 reserved 1 total pins 324
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 35 preliminary data sheet signal functional descriptions the following table provides a description of the i/o signals on the ppc405EZ. table 6. signal functional description (sheet 1 of 6) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 34 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 34 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes ethernet interface emccol collision signal from the phy. i 3.3v lvttl 5 emccrs carrier sense signal from the phy. i 3.3v lvttl 5 emcmdc management data clock to the phy. o 3.3v lvttl emcmdio management data i/o between the ethernet controller and the phy. i/o 3.3v lvttl emcrxclk input receive clock from the phy. i 3.3v lvttl rcvr emcrxdv receive data valid. i 3.3v lvttl 5 emcrxer receive error from the phy. i 3.3v lvttl rcvr emcrxd0:3 receive data from the phy. emcrxd3 is the msb. i 3.3v lvttl 5 emctxclk input transmit clock from the phy. i 3.3v lvttl emctxd0:3 transmit data to the phy. emctxd3 is the msb. o 3.3v lvttl emctxen transmit enable. o 3.3v lvttl emctxer transmit error to the phy. o 3.3v lvttl ieee 1588 networ k synchronization interface ieee_1588ts test signal. o 3.3v lvttl iic peripheral interface iic0sclk iic serial clock. i/o 3.3v iic 1, 5 iic0sdata iic serial data. i/o 3.3v iic 1, 5 interrupts interface irq0:4 interrupt requests. i 3.3v lvttl 1, 5 jtag interface tck test clock. i 3.3v lvttl rcvr w/pull-up 5 tdi test data in. i 3.3v lvttl 5 tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl 5 trst test reset. must be low at power-on to initialize the jtag controller and for normal operation of the ppc405EZ. i 3.3v lvttl rcvr w/pull-up 5
ppc405EZ ? powerpc 405EZ embedded processor 36 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet system interface sysclk system input clock. i 3.3v lvttl syserr machine check exception has occurred. o 3.3v lvttl sysreset main system reset. this signal may be driven by the ppc405EZ to cause a board level reset to occur. i 3.3v lvttl testen test enable. reserved for manufacturing lssd test. i 3.3v lvttl 5 debugen debug enable. i 3.3v lvttl 5 halt external request to stop the processor. i 3.3v lvttl 4 tmrclk processor timer external input. i 3.3v lvttl gpio000:03 general purpose i/o. all of the gp io signals are multiplexed with other signals. which signal a pi n is connected to depends on the setting of bits in the gpio registers. i/o 3.3v lvttl gpio004:05 i/o 3.3v lvttl 5 gpio006:08 i/o 3.3v lvttl gpio009 i/o 3.3v lvttl 4 gpio010:11 i/o 3.3v lvttl gpio012:19 i/o 3.3v lvttl 5 gpio019:27 i/o 3.3v lvttl gpio028:31 gpio100:12 i/o 3.3v lvttl 5 gpio113:14 i/o 3.3v lvttl gpio115:21 i/o 3.3v lvttl 5 trace interface trcclk trace interface clock. operates at half the cpu core frequency. i 3.3v lvttl ts1e ts2e even trace execution status. i 3.3v lvttl ts1o ts2o odd trace execution status. i 3.3v lvttl ts3:6 trace status. i 3.3v lvttl chameleon timer interface pwm_divclk divided-down clock. o 3.3v lvttl pwm_oe0 pwm 0 output enable input. i 3.3v lvttl 4 pwm_oe1:3 pwm 1:3 output enable input. i 3.3v lvttl pwm_tba time base a. i/o 3.3v lvttl pwm_1:15 pwm interface bus. i/o 3.3v lvttl 5 table 6. signal functional description (sheet 2 of 6) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 34 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 34 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 37 preliminary data sheet analog to digita l (adc) interface adc_in0:7 analog inputs. analog inputs to the adc should be referenced to adc_agnd and should not exceed the value of vref. i analog wide- wire receiver adc_intrig input trigger. i 3.3v lvttl adc_vref analog input reference voltage. allowable voltage range is 2v?adc_av dd . i analog wide- wire receiver digital to analog (dac) interface dac_cref reference voltage for the gate of the dac current sources. this voltage should be connected to the dac_av dd voltage with a 1nf filter capacitor at the signal pin. i analog wide- wire driver dac_ioutp analog positive output current. o analog wide- wire driver dac_iptrig input trigger. i 3.3v lvttl dac_irref analog input reference current. i analog wide- wire driver dac_vref analog band gap voltage reference input. allowable voltage range is 1.15v?1.26v, with a typical value of 1.174v. i analog wide- wire driver dac_gref reference voltage for the gate of the cascode device in the dac current sources. this voltage should be connected to the dac_av dd voltage with a 1nf filter capacitor at the signal pin. i analog wide- wire driver controller area network interface can0_rx receive input. i 3.3v lvttl rcvr w/pull-up 5 can0_tx transmit output. o 3.3v lvttl can0_txe transmit enable. o 3.3v lvttl can1_rx receive input. i 3.3v lvttl 5 can1_tx transmit output. o 3.3v lvttl can1_txe transmit enable. o 3.3v lvttl table 6. signal functional description (sheet 3 of 6) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 34 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 34 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405EZ ? powerpc 405EZ embedded processor 38 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet external peripheral interface cram_adv address valid signal for psram/cram support. o 3.3v lvttl cram_clk perclk gated for psram/cram support. o 3.3v lvttl peraddr04:31 memory address bus 4:31. o 3.3v lvttl busreq external plb bus request. o 3.3v lvttl perclk clock output. o 3.3v lvttl percs0:7 chip selects 0:7. o 3.3v lvttl perdata00:31 memory data bus 0:31. i/o 3.3v lvttl 5 peroe output enable. o 3.3v lvttl perready wait for psram/cram support. i 3.3v lvttl perrw read/write. o 3.3v lvttl perwbe0:3 write bus enable 0:3. o 3.3v lvttl dmaack external dma peripheral acknowledge. o 3.3v lvttl dmaeot/tc external dma peripheral end-of-transmi ssion/terminal count. i/o 3.3v lvttl 5 dmareq external peripheral dma request. i 3.3v lvttl 5 holdreq external request for bus access. i 3.3v lvttl holdack external request acknowledge. o 3.3v lvttl holdpri external bus request priority. i 3.3v lvttl nand flash interface nfale address latch enable. o 3.3v lvttl nfce0:3 cchip selects 0:3. o 3.3v lvttl nfcle command latch enable. o 3.3v lvttl nfdata0:7 data bits 0:7 i/o 3.3v lvttl nfrb read/busy. if low, indicates that read/erase command is in process. if high, indicates that the command is complete. i 3.3v lvttl nfre read enable. o 3.3v lvttl nfwe write enable. o 3.3v lvttl serial peripheral interface spi_clkout serial peripheral interface clock. o 3.3v lvttl spi_di master and slave input. i 3.3v lvttl 5 spi_do master and slave output. o 3.3v lvttl spi_ss0:3 slave select 0:3. o 3.3v lvttl spi_ss_in slave select input for multi-mast er collision detection. i 3.3v lvttl table 6. signal functional description (sheet 4 of 6) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 34 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 34 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 39 preliminary data sheet uart peripheral interface uart0_cts clear to send. i 3.3v lvttl uart0_dcd data carrier detect. i 3.3v lvttl uart0_dsr data set ready. i 3.3v lvttl uart0_dtr data terminal ready. o 3.3v lvttl uart0_ri ring indicator. i 3.3v lvttl uart0_rts request to send. o 3.3v lvttl uart0_rx receive data. i 3.3v lvttl 5 uart0_tx transmit data. o 3.3v lvttl uart1_rx receive data i 3.3v lvttl 5 uart1_tx transmit data o 3.3v lvttl usb interface usb1fclk 48 mhz clock for usb i 3.3v lvttl usb1dev0 device differential + data signal i/o 5v tolerant usb diff usb1dev0 device differential ? data signal i/o 5v tolerant usb diff usb1host0 host 0 differential + data signal i/o 5v tolerant usb diff usb1host0 host 0 differential ? data signal i/o 5v tolerant usb diff usb1host1 host 1 differential + data signal i/o 5v tolerant usb diff usb1host1 host 1 differential ? data signal i/o 5v tolerant usb diff table 6. signal functional description (sheet 5 of 6) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 34 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 34 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405EZ ? powerpc 405EZ embedded processor 40 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet power v dd logic v dd supply. na na na ov dd 1 non-ebc i/o v dd supply. na na na ov dd 2 ebc i/o v dd supply. na na na gnd system ground. na na na adc_av dd adc analog v dd supply. na analog wide- wire receiver na adc_agnd adc analog ground. na analog wide- wire receiver na dac_av dd dac analog v dd supply. it is recommended that this voltage be provided by means of a voltage supply and voltage plane separate from the logic voltage. na analog wide- wire receiver na dac_agnd dac analog ground. na analog wide- wire receiver na pll_av dd pll analog v dd supply. see ?absolut e maximum ratings? on page 41 for filter recommendations. na na na pll_agnd pll analog ground. na na na other pins reserved reserved pins. do not make voltage, ground, or signal connections to these pins. na na na table 6. signal functional description (sheet 6 of 6) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 34 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 34 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 41 preliminary data sheet ratings and specifications table 7. absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond thes e maximum ratings can cause permanent damage to the device. none of the performance s pecification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes supply voltage (internal logic) v dd 0 to +1.6 v non-ebc i/o supply voltage ov dd 1 0 to +3.6 v ebc i/o supply voltage ov dd 2 0 to +3.6 v 3 pll analog supply voltage pll_av dd 0 to +1.6 v adc analog supply voltage adc_av dd 0 to +3.465 v dac analog supply voltage dac_av dd 0 to +3.465 v input voltage (3.3v lvttl receivers) v in 0 to +3.6 v input voltage (5.0v lvttl receivers) v in 0 to +5.5 v storage temperature range t stg -55 to +150 c case temperature under bias t c -40 to +120 c junction temperature t jmax +125 c 1. all voltages are specifi ed with respect to gnd. 2. the analog voltages use for the system pll, the adc, and the dac can be derived from v dd and ov dd 1, but must be filtered as shown below before entering the ppc405EZ. use a separate filter for each voltage. the maximum value for adc_pll and dac_pll must be limited to the values shown in this table. 3. ov dd 2 must be limited to a maximum value of +3.3v if cram/psr am devices are attached to the ebc interface. this is a limitation imposed by the cram/ psram devices, not the ppc405EZ. v dd c1 pll_av dd l1 l1 ? murata blm18ag121sn1d c1 ? 0.1 f ceramic pll_agnd gnd ov dd 1 c1 adc_pll, dac_pll l1 l1 ? murata blm18ag121sn1d c1 ? 0.1 f ceramic adc_gnd, dac_gnd gnd c2 ? 0.01 f ceramic c2
ppc405EZ ? powerpc 405EZ embedded processor 42 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet thermal management the following heat sink was used in the above thermal analysis: aavid thermalloy, pn 79985 the heat sink is manufactured by: aavid thermalloy 70 commercial st. concord, nh 03301 usa tel: (603)224-9988 url: www.aavidthermalloy.com table 8. package thermal specifications the ppc405EZ is designed to operate within a case temperature range of -40c to +105c. thermal resistance values for the epbga packages in a convection environment ar e as follows: parameter symbol airflow ft/min (m/sec) unit 0 (0) 100 (0.51) 200 (1.02) 300 (1.52) 400 (2.02) 600 (3.03) junction-to-ambient thermal resistance without heat sink ja 29.3 24.1 22.9 22.4 22.0 21.6 c/w junction-to-ambient thermal resistance with heat sink ja 22.7 14.3 12.3 11.5 11.1 10.7 c/w resistance value junction-to-case thermal resistance jc 11.9 c/w junction-to-board thermal resistance jb 16.4 c/w notes: 1. values in the table are achieved with the following jedec standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers. 2. for a chip mounted on a card with at least one signal and two power planes, the foll owing relationships exist: a. case temperature, t c , is measured at top center of case surface with device soldered to circuit board. b. t a = t c ? px ca , where t a is ambient temperature and p is power consumption. c. t cmax = t jmax ? px jc , where t jmax is maximum junction temperat ure and p is power consumption. 3. values with a heat sink were achieved with a 38.1mm x 38.1mm x 16.5mm unit, attached to the chip using a 0.1mm thickness of adhesive having a thermal c onductivity of 1.3w/mk.
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 43 preliminary data sheet table 9. recommended dc operating conditions device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage v dd +1.425 +1.5 +1.575 v i/o supply voltage (for non-ebc i/o) ov dd 1 +3.0 +3.3 +3.6 v i/o supply voltage (for ebc i/o) ov dd 2 +3.0 +3.3 +3.6 (see note 1) v1 pll analog supply voltage pll_av dd +1.4 +1.5 +1.6 v adc analog supply voltage adc_av dd +3.135 +3.3 +3.465 v dac analog supply voltage dac_av dd +3.135 +3.3 +3.465 v i/o input low (3.3v lvttl) v il 0+0.8v i/o input high (3.3v lvttl) v ih +2.0 +3.6 v i/o output low (3.3v lvttl) v ol 0+0.4v i/o output high (3.3v lvttl) v oh +2.4 +3.6 v i/o high (usb, 5v tolerant) v oh +2.8 v i/o low (usb, 5v tolerant) v ol +0.3 v i/o input high (iic) v ih 0.7ov dd ov dd + 0.3 v i/o input low (iic) v il ? 0.3 +0.3ov dd v i/o output high (iic) v ih v i/o output low (iic) v ol 0+0.4v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current (with internal pull-down) i il2 0200 a i/o maximum allowable overshoot (3.3v lvttl) v mao +3.9 v i/o maximum allowable undershoot (3.3v lvttl) v mau ? 0.6 v case temperature t c ? 40 +105 c notes: 1. when using cram or psram memory on the ebc interface, this volta ge must be limited to a maximum of +3.3v. this is a limitatio n imposed by the cram/psram devices, not the ppc405EZ. table 10. input capacitance parameter symbol maximum unit notes 3.3v lvttl i/o c in1 1.9 pf usb 5v tolerant i/o c in2 3.2 pf iic i/o c in3 5.8 pf
ppc405EZ ? powerpc 405EZ embedded processor 44 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet test conditions clock timing and switching characteristic s are specified in accordance with minimum operating conditions shown in the table ?recommended dc operating conditions? on page 43. for all signals, ac spec ifications are characterized at t c = 85c with the 50pf test load shown in the figure to the right. table 11. typical dc power supply requirements frequency (mhz) +1.5v supply +3.3v supply total unit notes 166 0.81 0.24 1.05 w 1 266 0.97 0.25 1.22 w 1 333 1.13 0.29 1.42 w 2 416 1.2 0.28 1.48 w 3 table 12. dc power supply loads parameter symbol typical maximum unit notes v dd (+1.5v) active operating current i dd 425 815 ma 1 ov dd (+3.3v) active operating current i odd 60 95 ma 1 av dd (+1.5v) active operating current i add 20 35 ma 1 adc_avdd (3.3v) adc input current i adcdd 78ma1 dac_avdd (3.3v) dac input current i dacdd 78ma1 notes: 1. typical and maximum values ar e estimates and subject to change. output pin 50pf
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 45 preliminary data sheet figure 3. clocking waveform table 13. system clocking specifications symbol parameter min max units cpu pf c processor clock frequency (must be scf c ) 133.33 416 mhz sysclk input scf c frequency 33.33 100 mhz sct cs edge stability (phase jitter, cycle to cycle) na 0.1 ns sct ch input high time 0.6 na ns sct cl input low time 0.6 na ns sc rt rise time na 0.4 ns note: input slew rate = 1v/ns trcclk output tcf c clock output frequency pf c /2 mhz tct cs clock edge stability (phase jitter, cycle to cycle) 0.2 ns other clocks vcof c vco frequency 600 1333.33 mhz plbf c plb frequency 33 166 mhz opbf c opb frequency 33 83 mhz t cl t ch t c 2.0v 1.5v 0.8v
ppc405EZ ? powerpc 405EZ embedded processor 46 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet spread spectrum clocking care must be taken if using a spread spectrum clock generator (sscg) with the ppc405EZ. this controller uses a pll for clock generation inside the chip. the accuracy wi th which the pll follows the sscg is called tracking skew. the pll bandwidth and phase angle determine how much tracking skew exists between the sscg and the pll for a given frequency deviation and modulation freq uency. if using an sscg with the ppc405EZ the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc405EZ with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. ? the maximum frequency de viation must not exceed ? 3%, and the modulation frequency must not exceed 40khz. in some cases, on-board ppc405EZ peripherals impose more stringent requirements (see note 1). ? use the peripheral bus clock for logic that is synchron ous to the peripheral bus because this clock tracks the modulation. notes: 1. the serial port baud rates are synchronous to th e modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors beg in to occur, assuming that the connected device is running at precise baud rates. if an external serial clock is used, baud rate is unaffected by the modulation. 2. ethernet operation is unaffected. 3. iic operation is unaffected. caution: the system designer must ensure that any sscg used with the ppc405EZ meets these requirements and does not adversely affect other aspects of the system.
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 47 preliminary data sheet figure 4. input setup and hold timing waveform figure 5. output delay and float timing waveform table 14. peripheral interface i/o clock timings clock min max units emctxclk frequency 2.5 25 mhz emctxclk high time 35% of nominal ? ns emctxclk low time 35% of nominal ? ns emcrxclk frequency 2.5 25 mhz emcrxclk high time 35% of nominal ? ns emcrxclk low time 35% of nominal ? ns tmrclk na 100 mhz perclk 33 83 mhz tck na 20 mhz usb1fclk (48mhz 0.05%) 47.976 48.024 mhz pwm_tba na 83 mhz system clock t is t ih min min inputs valid 1.5v 1.5v valid t ov t oh min outputs system clock outputs t of min max max 1.5v 1.5v 1.5v
ppc405EZ ? powerpc 405EZ embedded processor 48 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet table 15. i/o specifications?all cpu speeds (sheet 1 of 2) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 8 02.3 standard. timing shown is with emac noise filter selected. 2. for all interfaces, i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. 3. maximum skew between iic output signals is 6ns. 4. maximum skew between all spi output signal s is 3ns. all spi inputs signals are la tched with less than 4ns of skew between channels. 5. maximum skew between all pwm output signals is 3.75ns. all pwm input signals are latched with less than 2.5ns of skew between channels. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (min) i/o l (min) ethernet interface emcrxd[0:3] 2.5 4 19.1 8.7 emcrxclk emctxd[0:3] 20 2 19.1 8.7 emctxclk emcrxer 2.5 4 na na na na emcrxclk emcmdio na na na na 19.1 8.7 async emcrxdv 2.5 4 na na na na emcrxclk emccrs na na 19.1 8.7 async emctxer 20 2 19.1 8.7 emctxclk emctxen 20 2 19.1 8.7 emctxclk emcmdc na na na na 19.1 8.7 async emccol na na 19.1 8.7 async internal peripheral interface iic0sclk na na na na iic 2.1 iic 2.1 na 3 iic0sdata na na na na iic 2.1 iic 2.1 na 3 uart0_cts na na na na na na na uart0_rts na na na na 19.1 8.7 na uart0_rx nanananananana uart0_tx na na na na 19.1 8.7 na uart1_rx nanananananana uart1_tx na na na na 19.1 8.7 na usb_fclk usb 2.1 usb 2.1 usb1dev0 usb 2.1 usb 2.1 usb1dev0 usb 2.1 usb 2.1 usb1host0 usb 2.1 usb 2.1 usb1host0 usb 2.1 usb 2.1 usb1host1 usb 2.1 usb 2.1 usb1host1 usb 2.1 usb 2.1 spi_clkout 19.1 8.7 4 spi_di na na 19.1 8.7 4 spi_do na na 19.1 8.7 4 spi_ss0:3 19.1 8.7 spi_ss_in 19.1 8.7 can0_rx nananana can0_tx 19.1 8.7 can0_txe 19.1 8.7 can1_rx nananana can1_tx na na 19.1 8.7 can1_txe 19.1 8.7 adc_in0:7 nananana
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 49 preliminary data sheet adc_intrig na na na na adc_vref na na na na dac_cref na na na na dac_ioutp nananana dac_iptrig 19.1 8.7 dac_irref nananana dac_vref na na na na dac_gref na na na na pwm_divclk 19.1 8.7 5 pwm_oe[0] 19.1 8.7 5 pwm_oe[1:3] 19.1 8.7 5 pwm_tba 19.1 8.7 5 pwm_1:15 19.1 8.7 5 ieee_1588ts 19.1 8.7 interrupts interface [irq0:4] 19.1 8.7 jtag interface tck nananananana tdi 22.50nanananatck tdo na na 25 0 19.1 8.7 tck tms 22.5 0 na na na na tck trst na na na na na na tck system interface gpio000:31 na na na na 19.1 8.7 gpio100:20 na na na na 19.1 8.7 halt 22.50nanananatck syserr na na 15 25.5 19.1 8.7 tck sysreset na na na na 19.1 8.7 async testen na na na na na na async debugen na na na na na na sysclk na na na na na na table 15. i/o specifications?all cpu speeds (sheet 2 of 2) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 8 02.3 standard. timing shown is with emac noise filter selected. 2. for all interfaces, i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. 3. maximum skew between iic output signals is 6ns. 4. maximum skew between all spi output signal s is 3ns. all spi inputs signals are la tched with less than 4ns of skew between channels. 5. maximum skew between all pwm output signals is 3.75ns. all pwm input signals are latched with less than 2.5ns of skew between channels. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (min) i/o l (min)
ppc405EZ ? powerpc 405EZ embedded processor 50 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet table 16. i/o specifications?416 mhz cpu notes: 1. perclk rising edge at package pin with a 10pf load tr ails the internal plb clock by approximately 0.8ns. 2. i/o h is specified at 2.4 v and i/o l is spec ified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) external peripheral interface perclk na na 19.1 8.7 na cram_clk na na 19.1 8.7 na cram_adv na na 7.2 2 19.1 8.7 perclk/ cram_clk peraddr04:31 na na 7.35 2.16 19.1 8.7 perclk/ cram_clk busreq na na 7.3 2.1 19.1 8.7 perclk/ cram_clk percs0:7 na na 7.3 2.1 19.1 8.7 perclk/ cram_clk perdata00:31 1.6 2.1 7.5 2.1 19.1 8.7 perclk/ cram_clk holdreq 1.6 2.1 na na na na perclk/ cram_clk holdack na na 7.3 2.1 19.1 8.7 perclk/ cram_clk holdpri 1.62.1nananana perclk/ cram_clk peroe na na 7.35 2.15 19.1 8.7 perclk/ cram_clk perready 1.6 2.1 na na na na perclk/ cram_clk perrw na na 7.35 2.15 19.1 8.7 perclk/ cram_clk perwbe0:3 na na 7.3 2.15 19.1 8.7 perclk/ cram_clk nfale 7.1 0.9 19.1 8.7 perclk/ cram_clk nfce0 7.1 0.9 19.1 8.7 perclk/ cram_clk nfcle 7.1 0.9 19.1 8.7 perclk/ cram_clk nfdata0:7 9.2 -0.7 7.1 0.9 19.1 8.7 perclk/ cram_clk nfrb 10 0 19.1 8.7 perclk/ cram_clk nfre 7.1 0.9 19.1 8.7 perclk/ cram_clk nfwe 7.1 0.9 19.1 8.7 perclk/ cram_clk dmaack na na 7.3 2.1 19.1 8.7 dmaeot/tc 19.1 8.7 dmareq 5 0.9 na na 19.1 8.7
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 51 preliminary data sheet initialization the following describes the method by which initial chip settings are es tablished when a system reset occurs. strapping when the sysreset input is driven low (system reset), the state of ce rtain i/o pins is read in order to enable default initial conditions before ppc405EZ start-up. the actual in stant of capture is the nearest system clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. the recommended pull-up is 3k to +3.3v, or 10k to +5v. the recommended pull-down is 1k to gnd. these pins are only used for stra p functions during reset. they are used for other signals during normal operation. the following tabl e lists the strapping pins along with their functions and strapping options. the signal names assigned to the pi ns for normal operation appear below the pin number. table 17. strapping pin assignments pin strapping function option f03 (gpio114) e03 (gpio112) d01 (gpio111) d02 (gpio110) initialize from ebc 8 bits wide 0000 16 bits wide 0001 32 bits wide 0010 initialize from nand flash 512 page, 3 addr cycle 0011 512 page, 4 addr cycle 0100 2k page, 4 addr cycle 0101 2k page, 5 addr cycle 0110 initialize from spi slow 0111 fast 1000 reserved na 1001 initialize from iic note: if reading of initialization data from the iic interface fails, the ppc405EZ defaults to strapping option 0010. na 1010 1011 1100 1101 1110 1111
ppc405EZ ? powerpc 405EZ embedded processor 52 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet revision log date version contents of modification 01/13/2006 1.08 initial distribution for review. 03/09/2006 1.09 misc. corrections. correct amcc address. add revision log. change three ebc signals to match previous chips (holdack, holdpri, and holdreq). 04/10/2006 1.10 misc. corrections. add pull-up/pull-down notes. update clock timings. correct bootstrap pin numbers. correct pin number swaps. add circuit types to signal descriptions. 04/21/2006 1.11 reduce recommended logic voltage range by 0.025v. add 266mhz and 333mhz cpu speeds. allow 3.3v power supply for adc and dac. add output currents to i/o tables. correct recommended operating conditions. remove 5v tolerant input current curve. add output current values (based on i/o circuit type) to i/o tables correct filter circuit component units-of-measure from m to . 05/12/2006 1.12 correct adc_in6 and adc_in7 pins assignment. correct ebc_dbus24 and ebc_dbus25 pins assignment. change signal name ni_divclk to pwm_divclk. add typical dc power requirements. 06/13/2006 1.13 split ov dd voltage pins into two sets so ebc voltage ca n be different from other i/o if necessary. update from engineering review. 07/18/2006 1.14 timing updates. 08/8/2006 1.15 chameleon timer and ieee 1588 ptp updates. add package thermal data. 08/30/2006 1.16 analog voltage filter updates. part number updates. 09/05/2006 1.17 remove te package and references to ?industrial? from thermal package data. remove watermark and change status to preliminary. add heat sink data and increase case temperature range to +105 c. 09/18/2006 1.18 change minimum cpu frequency to 133.33mhz. add dc power supply current load values. 10/18/2006 1.19 change pin assignments for the ethernet tx and rx data signals. alter prefixes and remove ex traneous characters from some signal names to make them consistent with the um and previous chips. t here are no functional or pin (ball) number changes. correct jtag id. remove can disable option. reduce maximum spi speed. change power specifications in description. add link to amcc partners supplying probes. deleted internal clock signal timing table. added perclk signal to exter nal peripheral timing table. restrict adc and dac analog voltage filters to ov dd 1. 02/07/2007 1.20 typographical updates
ppc405EZ ? powerpc 405EZ embedded processor revision 1.27 - august 22, 2007 amcc proprietary 53 preliminary data sheet 02/20/2007 1.21 the vcof c minimal value in the system clock specif ication in table 13: changed to 600 mhz instead of 66 02/21/2007 1.22 changes to the uart section and the ethernet section 02/27/2007 1.23 added a sentence to the nand flash controller section 03/05/2007 1.24 change picture on page 16. 04/02/2007 1.25 added a overline on the signal cram_adv. 04/23/2007 1.26 changed the pvr value on page 4 08/22/2007 1.27 added missing information to table 14. date version contents of modification
ppc405EZ ? powerpc 405EZ embedded processor 54 amcc proprietary revision 1.27 - august 22, 2007 preliminary data sheet applied micro circuits corporation 215 moffett park drive, sunnyvale, ca 94089 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com amcc reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. please consult amcc?s term and condi tions of sale for its warranties and ot her terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the info rmation is current. amcc does not assume any lia - bility arising out of the application or use of any product or circuit described herein, neither does it convey any license und er its patent rights nor the rights of others. amcc reserves the ri ght to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2007 applied micro circuits corporation.

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